module cu(Q, Z, G,reset,clk,signal);
input G, clk, reset, Z;
reg [2:0] state, nextstate;
output reg [2:0] signal;
parameter S0 = 3'b000;
parameter S1 = 3'b001;
parameter S2 = 3'b011;
parameter S3 = 3'b010;
parameter S4 = 3'b110;
parameter S5 = 3'b111;
parameter S6 = 3'b101;
always @(posedge clk)
if(reset) state <= S0;
else state <= nextstate;

reg change;

always @(*)
case(state)
S0: if(G==0)begin nextstate=S1; end
    else nextstate = S0;
S1: if(G) begin nextstate=S2; signal = 3'b001; end
    else nextstate = S1;
S2: if(G==0)begin nextstate=S3; end
    else nextstate = S2;
S3: if(G) begin nextstate=S4; signal = 3'b011; end
    else nextstate = S3;
S4: if(Q) nextstate = S5;
    else nextstate = S6;
S5: if(1) begin nextstate = S6; signal = 3'b010; end
default: if(Z) begin nextstate = S0; signal = 3'b110; end
         else 
         begin 
             signal = 3'b110;
             if(Q) nextstate = S5;
             else nextstate = S6;
         end
endcase 
endmodule
